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1.35v ddr3 sdram rdimm mt18kdf25672pdz C 2gb mt18kdf51272pdz C 4gb features ? ddr3 functionality and operations supported as de- fined in the component data sheet ? 240-pin, registered dual in-line memory module (rdimm) ? fast data transfer rates: pc3-12800, pc3-10600, pc3-8500, or pc3-6400 ? 2gb (256 meg x 72), 4gb (512 meg x 72) ? v dd = 1.35v (1.283v to 1.45v) ? backward compatible to v dd = +1.5v 0.075v ? v ddspd = +3.0v to +3.6v ? supports ecc error detection and correction ? nominal and dynamic on-die termination (odt) for data, strobe, and mask signals ? dual rank ? on-board i 2 c temperature sensor with integrated se- rial presence-detect (spd) eeprom ? fixed burst chop (bc) of 4 and burst length (bl) of 8 via the mode register set (mrs) ? selectable bc4 or bl8 on-the-fly (otf) ? gold edge contacts ? halogen-free ? fly-by topology ? terminated control, command, and address bus figure 1: 240-pin rdimm (mo-269 r/c l) pcb height: 18.75mm (0.738 in) options marking ? operating temperature C commercial (0c t a +70c) none ? package C 240-pin dimm (halogen-free) z ? frequency/cas latency C 1.25ns @ cl = 11 (ddr3-1600) -1g6 C 1.5ns @ cl = 9 (ddr3-1333) -1g4 C 1.87ns @ cl = 7 (ddr3-1066) -1g1 C 1.87ns @ cl = 8 (ddr3-1066) 1 -1g0 C 2.5ns @ cl = 5 (ddr3-800) 1 -80c C 2.5ns @ cl = 6 (ddr3-800) 1 -80b note: 1. not recommended for new designs. table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 11 cl = 10 cl = 9 cl = 8 cl = 7 cl = 6 cl = 5 -1g6 pc3-12800 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125 -1g4 pc3-10600 C 1333 1333 1066 1066 800 667 13.125 13.125 49.125 -1g1 pc3-8500 C C C 1066 1066 800 667 13.125 13.125 50.625 -1g0 pc3-8500 C C C 1066 C 800 667 15 15 52.5 -80c pc3-6400 C C C C C 800 800 12.5 12.5 50 -80b pc3-6400 C C C C C 800 667 15 15 52.5 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm features pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
table 2: addressing parameter 2gb 4gb refresh count 8k 8k row address 16k a[13:0] 32k a[14:0] device bank address 8 ba[2:0] 8 ba[2:0] device configuration 1gb (128 meg x 8) 2gb (256 x 8) column address 1k a[9:0] 1k a[9:0] module rank address 2 s#[1:0] 2 s#[1:0] table 3: part numbers and timing parameters C 2gb modules base device: mt41k128m8jp, 1 1gb ddr3 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt18kdf25672pdz-1g6__ 2gb 256 meg x 72 12.8 gb/s 1.25ns/1600 mt/s 11-11-11 mt18kdf25672pdz-1g4__ 2gb 256 meg x 72 10.6 gb/s 1.5ns/1333 mt/s 9-9-9 mt18kdf25672pdz-1g1__ 2gb 256 meg x 72 8.5 gb/s 1.87ns/1066 mt/s 7-7-7 notes: 1. the data sheet for the base device can be found on microns web site. 2. all part numbers end with a two-place code (not shown) that designates component and pcb revisions. con- sult factory for current revision codes. example: mt18kdf25672pdz-1g4 f1. table 4: part numbers and timing parameters C 4gb modules base device: mt41k256m8jp, 1 2gb ddr3 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt18kdf51272pdz-1g6__ 4gb 512 meg x 72 12.8 gb/s 1.25ns/1600 mt/s 11-11-11 mt18kdf51272pdz-1g4__ 4gb 512 meg x 72 10.6 gb/s 1.5ns/1333 mt/s 9-9-9 mt18kdf51272pdz-1g1__ 4gb 512 meg x 72 8.5 gb/s 1.87ns/1066 mt/s 7-7-7 notes: 1. the data sheet for the base device can be found on microns web site. 2. all part numbers end with a two-place code (not shown) that designates component and pcb revisions. con- sult factory for current revision codes. example: mt18kdf51272pdz-1g4 f1. 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm features pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
pin assignments and descriptions table 5: pin assignments 240-pin ddr3 rdimm front 240-pin ddr3 rdimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 v refdq 31 dq25 61 a2 91 dq41 121 v ss 151 v ss 181 a1 211 v ss 2 v ss 32 v ss 62 v dd 92 v ss 122 dq4 152 dm3/ tdqs12 182 v dd 212 dm5/ tdqs14 3 dq0 33 dqs3# 63 nc 93 dqs5# 123 dq5 153 nf/ tdqs12# 183 v dd 213 nf/ tdqs14# 4 dq1 34 dqs3 64 nc 94 dqs5 124 v ss 154 v ss 184 ck0 214 v ss 5 v ss 35 v ss 65 v dd 95 v ss 125 dm0/ tdqs9 155 dq30 185 ck0# 215 dq46 6 dqs0# 36 dq26 66 v dd 96 dq42 126 nf/ tdqs9# 156 dq31 186 v dd 216 dq47 7 dqs0 37 dq27 67 v refca 97 dq43 127 v ss 157 v ss 187 event# 217 v ss 8 v ss 38 v ss 68 par_in 98 v ss 128 dq6 158 cb4 188 a0 218 dq52 9 dq2 39 cb0 69 v dd 99 dq48 129 dq7 159 cb5 189 v dd 219 dq53 10 dq3 40 cb1 70 a10 100 dq49 130 v ss 160 v ss 190 ba1 220 v ss 11 v ss 41 v ss 71 ba0 101 v ss 131 dq12 161 dm8/ tdqs17 191 v dd 221 dm6/ tdqs15 12 dq8 42 dqs8# 72 v dd 102 dqs6# 132 dq13 162 nf/ tdqs17# 192 ras# 222 nf/ tdqs15# 13 dq9 43 dqs8 73 we# 103 dqs6 133 v ss 163 v ss 193 s0# 223 v ss 14 v ss 44 v ss 74 cas# 104 v ss 134 dm1/ tdqs10 164 cb6 194 v dd 224 dq54 15 dqs1# 45 cb2 75 v dd 105 dq50 135 nu/ tdqs10# 165 cb7 195 odt0 225 dq55 16 dqs1 46 cb3 76 s1# 106 dq51 136 v ss 166 v ss 196 a13 226 v ss 17 v ss 47 v ss 77 odt1 107 v ss 137 dq14 167 nu 197 v dd 227 dq60 18 dq10 48 v tt 78 v dd 108 dq56 138 dq15 168 reset# 198 nc 228 dq61 19 dq11 49 v tt 79 nc 109 dq57 139 v ss 169 cke1 199 v ss 229 v ss 20 v ss 50 cke0 80 v ss 110 v ss 140 dq20 170 v dd 200 dq36 230 dm7/ tdqs16 21 dq16 51 v dd 81 dq32 111 dqs7# 141 dq21 171 a15 201 dq37 231 nf/ tdqs16# 22 dq17 52 ba2 82 dq33 112 dqs7 142 v ss 172 a14 202 v ss 232 v ss 23 v ss 53 err_out# 83 v ss 113 v ss 143 dm2/ tdqs11 173 v dd 203 dm4/ tdqs13 233 dq62 24 dqs2# 54 v dd 84 dqs4# 114 dq58 144 nf/ tdqs11# 174 a12 204 nf/ tdqs13# 234 dq63 25 dqs2 55 a11 85 dqs4 115 dq59 145 v ss 175 a9 205 v ss 235 v ss 26 v ss 56 a7 86 v ss 116 v ss 146 dq22 176 v dd 206 dq38 236 v ddspd 27 dq18 57 v dd 87 dq34 117 sa0 147 dq23 177 a8 207 dq39 237 sa1 28 dq19 58 a5 88 dq35 118 scl 148 v ss 178 a6 208 v ss 238 sda 29 v ss 59 a4 89 v ss 119 sa2 149 dq28 179 v dd 209 dq44 239 v ss 30 dq24 60 v dd 90 dq40 120 v tt 150 dq29 180 a3 210 dq45 240 v tt 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm pin assignments and descriptions pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 6: pin descriptions symbol type description a[15:0] input address inputs: provide the row address for activate commands, and the column ad- dress and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge com- mand to determine whether the precharge applies to one bank (a10 low, bank selec- ted by ba[2:0]) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba. a12 is also used for bc4/bl8 identification as bl on-the-fly during cas commands. the address inputs also provide the op-code during the mode register com- mand set. a[13:0] address the 1gb ddr3 devices. a[15:14] are needed to calculate parity on the command/address bus. ba[2:0] input bank address inputs: ba[2:0] define the device bank to which an activate, read, write, or precharge command is being applied. ba[2:0] define which mode register (mr0, mr1, mr2, and mr3) is loaded during the load mode command. ba[2:0] are used as part of the parity calculation. ck0, ck0# input clock: ck and ck# are differential clock inputs. all control, command, and address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. cke[1:0] input clock enable: cke enables (registered high) and disables (registered low) internal cir- cuitry and clocks on the dram. dm[8:0], (tdqs[17:9], tdqs#[17:9]) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high, along with the input data, during a write access. dm is sampled on both edges of the dqs. although the dm pins are input-only, the dm loading is designed to match that of the dq and dqs pins. when tdqs is enabled, dm is disabled and tdqs and tdqs# provide termination resistance, otherwise the tdqs# pins are no function. odt[1:0] input on-die termination: odt enables (registered high) and disables (registered low) termi- nation resistance internal to the dram. when enabled in normal operation, odt is applied only to the following pins: dq, dqs, dqs#, and dm. the odt input will be ignor- ed if disabled via the load mode command. par_in input parity input: parity bit for the address, ras#, cas#, and we#. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being en- tered. reset# input (lvcmos) reset: reset# is an active low cmos input referenced to v ss . the reset# input receiver is a cmos input defined as a rail-to-rail signal with dc high 0.8 v dd and dc low 0.2 v dd . s#[1:0] input chip select: s# enables (registered low) and disables (registered high) the command decoder. sa[2:0] input serial address inputs: these pins are used to configure the temperature sensor/spd ee- prom address range on the i 2 c bus. scl input serial clock for temperature sensor/spd eeprom: scl is used to synchronize commu- nication to and from the temperature sensor/spd eeprom. cb[7:0] i/o check bits: data used for ecc. dq[63:0] i/o data input/output: bidirectional data bus. 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm pin assignments and descriptions pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 6: pin descriptions (continued) symbol type description dqs[8:0], dqs#[8:0] i/o data strobe: dqs and dqs# are differential data strobes. output with read data. edge- aligned with read data. input with write data. center-aligned with write data. dqs# is used only when the differential data strobe mode is enabled via the load mode command. sda i/o serial data: sda is a bidirectional pin used to transfer addresses and data into and out of the temperature sensor/spd eeprom on the module on the i 2 c bus. err_out# output (open drain) parity error output: parity error found on the command and address bus. event# output (open drain) temperature event: the event# pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded. v dd supply power supply: 1.5v 0.075v. the component v dd and v ddq are connected to the mod- ule vdd. v ddspd supply temperature sensor/spd eeprom power supply: +3.0v to +3.6v. v refca supply reference voltage: control, command, and address (v dd /2). v refdq supply reference voltage: dq, dm (v dd /2). v ss supply ground. v tt supply termination voltage: used for control, command, and address (v dd /2). nc C no connect: these pins are not connected on the module. nf C no function: connected within the module, but provide no functionality. nu C not usable: no external connections allowed. 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm pin assignments and descriptions pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
dq map table 7: component-to-module dq map, front component reference number component dq module dq module pin number component reference number component dq module dq module pin number u1 0 2 9 u2 0 10 18 1 1 4 1 9 13 2 3 10 2 11 19 3 0 3 3 8 12 4 6 128 4 14 137 5 4 122 5 12 131 6 7 129 6 15 138 7 5 123 7 13 132 u3 0 18 27 u4 0 26 36 1 17 22 1 25 31 2 19 28 2 27 37 3 16 21 3 24 30 4 22 146 4 30 155 5 20 140 5 28 149 6 23 147 6 31 156 7 21 141 7 29 150 u5 0 cb2 45 u7 0 34 87 1 cb1 40 1 33 82 2 cb3 46 2 35 88 3 cb0 39 3 32 81 4 cb6 164 4 38 206 5 cb4 158 5 36 200 6 cb7 165 6 39 207 7 cb5 159 7 37 201 u8 0 42 96 u9 0 50 105 1 41 91 1 49 100 2 43 97 2 51 106 3 40 90 3 48 99 4 46 215 4 54 224 5 44 209 5 52 218 6 47 216 6 55 225 7 45 210 7 53 219 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm dq map pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 7: component-to-module dq map, front (continued) component reference number component dq module dq module pin number component reference number component dq module dq module pin number u10 0 58 114 1 57 109 2 59 115 3 56 108 4 62 233 5 60 227 6 63 234 7 61 228 table 8: component-to-module dq map, back component reference number component dq module dq module pin number component reference number component dq module dq module pin number u11 0 57 109 u12 0 49 100 1 58 114 1 50 105 2 56 108 2 48 99 3 69 115 3 51 106 4 61 228 4 53 219 5 63 234 5 55 225 6 60 227 6 52 218 7 62 233 7 54 224 u13 0 41 91 u14 0 33 82 1 42 96 1 34 87 2 40 90 2 32 81 3 43 97 3 35 88 4 45 210 4 37 201 5 47 216 5 39 207 6 44 209 6 36 200 7 46 215 7 38 206 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm dq map pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 8: component-to-module dq map, back (continued) component reference number component dq module dq module pin number component reference number component dq module dq module pin number u16 0 cb1 40 u17 0 25 31 1 cb2 45 1 26 36 2 cb0 39 2 24 30 3 cb3 46 3 27 37 4 cb5 159 4 29 150 5 cb7 165 5 31 156 6 cb4 158 6 28 149 7 cb6 164 7 30 155 u18 0 17 22 u19 0 9 13 1 18 27 1 10 18 2 16 21 2 8 12 3 19 28 3 11 19 4 21 141 4 13 132 5 23 147 5 15 138 6 20 140 6 12 131 7 22 146 7 14 137 u20 0 1 4 1 2 9 2 0 3 3 3 10 4 5 123 5 7 129 6 4 122 7 6 128 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm dq map pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
functional block diagram figure 2: functional block diagram dq dq dq dq dq dq dq dq zq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm/ nu/ cs# dqs dqs# rdqs rdqs# u1 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u20 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dm/ nu/ cs# dqs dqs# rdqs rdqs# u7 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u14 dqs0 dqs0# dm0/dqs9 nf/tdqs9# dqs4 dqs4# dm4/dqs13 nf/tdqs13# dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm/ nu/ cs# dqs dqs# rdqs rdqs# u2 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u19 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dm/ nu/ cs# dqs dqs# rdqs rdqs# u8 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u13 dqs1 dqs1# dm1/dqs10 nf/tdqs10# dqs5 dqs5# dm5/dqs14 nf/tdqs14# dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dm/ nu/ cs# dqs dqs# rdqs rdqs# u3 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u18 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dm/ nu/ cs# dqs dqs# rdqs rdqs# u9 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u12 dqs2 dqs2# dm2/dqs11 nf/tdqs11# dqs6 dqs6# dm6/dqs15 nf/tdqs15# dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dm/ nu/ cs# dqs dqs# rdqs rdqs# u4 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u17 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dm/ nu/ cs# dqs dqs# rdqs rdqs# u10 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u11 dqs3 dqs3# dm3/dqs12 nf/tdqs12# dqs7 dqs7# dm7/dqs16 nf/tdqs16# cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dm/ nu/ cs# dqs dqs# rdqs rdqs# u5 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u16 dqs8 dqs8# dm8/dqs17 nf/tdqs17# dq dq dq dq dq dq dq dq zq dq dq dq dq dq dq dq dq zq dq dq dq dq dq dq dq dq zq dq dq dq dq dq dq dq dq zq dq dq dq dq dq dq dq dq zq dq dq dq dq dq dq dq dq zq dq dq dq dq dq dq dq dq zq dq dq dq dq dq dq dq dq zq rs1# rs0# r e g i s t e r a n d p l l s0# s1# ba[2:0] a[15:0] ras# cas# we# cke0 cke1 odt0 odt1 par_in reset# ck0 ck0# rs0#: rank 0 rs1#: rank 1 rba[2:0]: ddr3 sdram ra[13:0]: ddr3 sdram rras#: ddr3 sdram rcas#: ddr3 sdram rwe#: ddr3 sdram rcke0: rank 0 rcke1: rank 1 rodt0: rank 0 rodt1: rank 1 err_out# u6 v refca v ss ddr3 sdram ddr3 sdram v dd ddr3 sdram v ddspd temperature sensor/spd eeprom v tt ddr3 sdram ddr3 sdram v refdq ck ck# ddr3 sdram ddr3 sdram rs#, rcke, ra[13:0], rras#, rcas#, rwe#, rodt, rba[2:0] ck ck# zq zq zq zq zq zq zq zq zq rank 0: u1Cu5, u7Cu10 rank 1: u11Cu14, u16Cu20 clock, control, command, and address line terminations: ddr3 sdram v tt ddr3 sdram v dd u15 a0 temperature sensor/ spd eeprom a1 a2 sa0 sa1 sda scl evt event# sa2 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss note: 1. the zq ball on each ddr3 component is connected to an external 240 1% resistor that is tied to ground. it is used for the calibration of the components odt and output driver. 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm functional block diagram pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
general description ddr3 sdram modules are high-speed, cmos dynamic random access memory mod- ules that use internally configured 8-bank ddr3 sdram devices. ddr3 sdram mod- ules use ddr architecture to achieve high-speed operation. ddr3 architecture is essentially an 8 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr3 sdram module effectively consists of a single 8 n -bit-wide, one-clock-cycle data transfer at the internal dram core and eight corresponding n-bit-wide, one-half-clock-cycle data trans- fers at the i/o pins. ddr3 modules use two sets of differential signals: dqs, dqs# to capture data and ck and ck# to capture commands, addresses, and control signals. differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. fly-by topology ddr3 modules use faster clock speeds than earlier ddr technologies, making signal quality more important than ever. for improved signal quality, the clock, control, com- mand, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each dram is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). inherent to fly-by topology, the timing skew between the clock and dqs signals can be easily accounted for by using the write-leveling feature of ddr3. registering clock driver operation registered ddr3 sdram modules use a registering clock driver device consisting of a register and a phase-lock loop (pll). the device complies with the jedec standard definition of the sste32882 registering clock driver with parity and quad chip se- lects for ddr3 rdimm applications. the register section of the registering clock driver latches command and address input signals on the rising clock edge. the pll section of the registering clock driver receives and redrives the differential clock signals (ck, ck#) to the ddr3 sdram devices. the register(s) and pll reduce clock, control, command, and address signals loading by iso- lating dram from the system controller. parity operations the registering clock driver can accept a parity bit from the systems memory control- ler, providing even parity for the control, command, and address bus. parity errors are flagged on the err_out# pin. systems not using parity are expected to function without issue if par_in and err_out# are left as no connects to the system. 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm general description pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
temperature sensor with serial presence-detect eeprom thermal sensor operations the temperature from the integrated thermal sensor is monitored and converts into a digital word via the i 2 c bus. system designers can use the user-programmable registers to create a custom temperature-sensing solution based on system requirements. pro- gramming and configuration details comply with jedec standard no. 21-c page 4.7-1 definition of the tse2002av, serial presence detect with temperature sensor. serial presence-detect eeprom operation ddr3 sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are programmed by micron to comply with je- dec standard jc-45 appendix x: serial presence detect (spd) for ddr3 sdram modules. these bytes identify module-specific timing parameters, configuration infor- mation, and physical attributes. user-specific information can be written into the remaining 128 bytes of storage. read/write operations between the system (master) and the eeprom (slave) device occur via an i 2 c bus. write protect (wp) is connected to vss, permanently disabling hardware write protect. for further information please refer to micron technical note tn-04-42, "memory module serial presence-detect." 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm general description pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
electrical specifications stresses greater than those listed may cause permanent damage to the module. this is a stress rating only, and functional operation of the module at these or any other condi- tions outside those indicated in each devices data sheet is not implied. exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. table 9: absolute maximum ratings symbol parameter min max units v dd v dd supply voltage relative to v ss C0.4 +1.975 v v in , v out voltage on any pin relative to v ss C0.4 +1.975 v table 10: operating conditions symbol parameter min nom max units notes v dd v dd supply voltage 1.283 1.35 1.45 v i vtt termination reference current from v tt C600 C +600 ma v tt termination reference voltage (dc) C command/address bus 0.49 v dd - 20mv 0.5 v dd 0.51 v dd + 20mv v 1 i i input leakage current; any input 0v v in v dd ; v ref input 0v v in 0.95v (all other pins not under test = 0v) address in- puts, ras#, cas#, we#, s#, cke, odt, ba, ck, ck# tbd tbd tbd a dm C4 0 +4 i oz output leakage current; 0v v out v dd ; dq and odt are disabled; odt is high dq, dqs, dqs# C10 0 +10 a i vref v vref supply leakage current; v vrefdq = v dd /2 or v vrefca = v dd /2 (all other pins not under test = 0v) C18 0 +18 a t a module ambient operating temperature commercial 0 C +70 c 2, 3 t c ddr3 sdram compo- nent case operating temperature commercial 0 C +95 c 2, 3, 4 notes: 1. v tt termination voltage in excess of the stated limit will adversely affect the command and address signals voltage margin and will reduce timing margins. 2. t a and t c are simultaneous requirements. 3. for further information, refer to technical note tn-00-08: thermal applications, available on microns web site. 4. the refresh rate is required to double when 85c < t c 95c. 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm electrical specifications pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
dram operating conditions recommended ac operating conditions are given in the ddr3 component data sheets. component specifications are available on microns web site. module speed grades cor- relate with component speed grades, as shown below. table 11: module and component speed grades ddr3 components may exceed the listed module speed grades; module may not be available in all listed speed grades module speed grade component speed grade -1g6 -125 -1g4 -15e -1g1 -187e -1g0 -187 -80c -25e -80b -25 design considerations simulations micron memory modules are designed to optimize signal integrity through carefully de- signed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good signal integrity starts at the system level. mi- cron encourages designers to simulate the signal characteristics of the systems memo- ry bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram, not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to en- sure the required supply voltage is maintained. 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm electrical specifications pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
i dd specifications table 12: ddr3 i dd specifications and conditions C 2gb values are for the mt41k128m8jp ddr3 sdram only and are computed from values specified in the 1gb (128 meg x 8) component data sheet parameter symbol 1600 1333 1066 units operating current 0: one bank activate-to-pre- charge i dd0 1 tbd tbd 945 ma operating current 1: one bank activate-to-read-to- precharge i dd1 1 tbd tbd 1080 ma precharge power-down current: slow exit i dd2p 2 tbd tbd 180 ma precharge power-down current: fast exit i dd2p 2 tbd tbd 450 ma precharge quiet standby current i dd2q 2 tbd tbd 810 ma precharge standby current i dd2n 2 tbd tbd 900 ma precharge stanby odt current i dd2nt 1 tbd tbd 720 ma active power-down current i dd3p 2 tbd tbd 540 ma active power-down current i dd3p 2 tbd tbd 540 ma active standby current i dd3n 2 tbd tbd 900 ma burst read operating current i dd4r 1 tbd tbd 1395 ma burst write operating current i dd4w 1 tbd tbd 1350 ma refresh current i dd5b 2 tbd tbd 3690 ma self refresh temperature current: max t c = 85c i dd6 2 tbd tbd 108 ma self refresh temperature current (srt-enabled): max t c = 95c i dd6et 2 tbd tbd 162 ma all banks interleaved read current i dd7 1 tbd tbd 3285 ma reset current i dd8 1 tbd tbd 216 ma notes: 1. one module rank in the active i dd , the other rank in i dd2p (slow exit). 2. all ranks in this i dd condition. table 13: ddr3 i dd specifications and conditions C 4gb values are for the mt41k256m8jp ddr3 sdram only and are computed from values specified in the 2gb (128 meg x 8) component data sheet parameter symbol 1600 1333 1066 units operating current 0: one bank activate-to-pre- charge i dd0 1 tbd tbd tbd ma operating current 1: one bank activate-to-read-to- precharge i dd1 1 tbd tbd tbd ma precharge power-down current: slow exit i dd2p 2 tbd tbd tbd ma precharge power-down current: fast exit i dd2p 2 tbd tbd tbd ma precharge quiet standby current i dd2q 2 tbd tbd tbd ma precharge standby current i dd2n 2 tbd tbd tbd ma precharge stanby odt current i dd2nt 1 tbd tbd tbd ma 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm electrical specifications pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 13: ddr3 i dd specifications and conditions C 4gb (continued) values are for the mt41k256m8jp ddr3 sdram only and are computed from values specified in the 2gb (128 meg x 8) component data sheet parameter symbol 1600 1333 1066 units active power-down current i dd3p 2 tbd tbd tbd ma active power-down current i dd3p 2 tbd tbd 540 ma active standby current i dd3n 2 tbd tbd tbd ma burst read operating current i dd4r 1 tbd tbd tbd ma burst write operating current i dd4w 1 tbd tbd tbd ma refresh current i dd5b 2 tbd tbd tbd ma self refresh temperature current: max t c = 85c i dd6 2 tbd tbd tbd ma self refresh temperature current (srt-enabled): max t c = 95c i dd6et 2 tbd tbd tbd ma all banks interleaved read current i dd7 1 tbd tbd tbd ma reset current i dd8 1 tbd tbd tbd ma notes: 1. one module rank in the active i dd , the other rank in i dd2p (slow exit). 2. all ranks in this i dd condition. 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm electrical specifications pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
registering clock driver specifications table 14: registering clock driver electrical characteristics sste32882 devices or equivalent symbol parameter pins min nom max units v dd dc supply voltage C 1.425 1.5 1.575 v v ref dc reference voltage C 0.49 v dd - 20mv 0.5 v dd 0.51 v dd + 20mv v v tt dc termination voltage C 0.49 v dd - 20mv 0.5 v dd 0.51 v dd + 20mv v v ih(ac) ac high-level input voltage control, command, address v ref + 175mv C v dd + 400mv v v il(ac) ac low-level input voltage control, command, address C0.4 C v ref - 175mv v v ih(dc) dc high-level input voltage control, command, address v ref + 100mv C v dd + 0.4 v v il(dc) dc low-level input voltage control, command, address C0.4 C v ref - 100mv v v ih(cmos) high-level input voltage reset#, mirror 0.65 v dd C v dd v v il(cmos) low-level input voltage reset#, mirror 0 C 0.35 v dd v v ix(ac) differential input cross point voltage range ck, ck#, fbin, fbin# 0.5 v dd - 175mv 0.5 v dd 0.5 v dd + 175mv v v id(ac) differential input voltage ck, ck# 350 C v dd + tbd mv i oh high-level output current err_out# C C tbd ma i ol low-level output current err_out# tbd C tbd ma note: 1. timing and switching specifications for the register listed are critical for proper opera- tion of the ddr3 sdram rdimms. these are meant to be a subset of the parameters for the specific device used on the module. 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm registering clock driver specifications pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
temperature sensor with serial presence-detect eeprom the temperature sensor continuously monitors the modules temperature and can be read back at any time over the i 2 c bus shared with the spd eeprom. table 15: temperature sensor with serial presence-detect eeprom operating conditions parameter/condition symbol min max units supply voltage v ddspd +3.0 +3.6 v supply current: v dd = 3.3v i dd C +2.0 ma input high voltage: logic 1; scl, sda v ih +1.45 v ddspd + 1 v input low voltage: logic 0; scl, sda v il C +0.55 v output low voltage: i out = 2.1ma v ol C +0.4 v input current i in C5.0 +5.0 a temperature sensing range C C40 +125 c temperature sensor accuracy (class b) C C1.0 +1.0 c table 16: sensor and eeprom serial interface timing parameter/condition symbol min max units time bus must be free before a new transition can start t buf 4.7 C s sda fall time t f 20 300 ns sda rise time t r C 1,000 ns data hold time t hd:dat 200 900 ns start condition hold time t h:sta 4.0 C s clock high period t high 4.0 50 s clock low period t low 4.7 C s scl clock frequency t scl 10 100 khz data setup time t su:dat 250 C ns start condition setup time t su:sta 4.7 C s stop condition setup time t su:sto 4.0 C s event# pin the temperature sensor also adds the event# pin (open drain). not used by the spd eeprom, event# is a temperature sensor output used to flag critical events that can be set up in the sensors configuration register. event# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. the open-drain output of event# under the three separate operating modes is illustrated below. event thresholds are programmed in the 0x01 reg- ister using a hysteresis. the alarm window provides a comparison window, with upper and lower limits set in the alarm upper boundary register and the alarm lower boun- dary register, respectively. when the alarm window is enabled, event# will trigger whenever the temperature is outside the min or max values set by the user. 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
the interrupt mode enables software to reset event# after a critical temperature thresh- old has been detected. threshold points are set in the configuration register by the user. this mode triggers the critical temperature limit and both the min and max of the tem- perature window. the compare mode is similar to the interrupt mode, except event# cannot be reset by the user and only returns to the logic high state when the temperature falls below the programmed thresholds. critical temperature mode triggers event# only when the temperature has exceeded the programmed critical trip point. when the critical trip point has been reached, the temperature sensor goes into comparator mode, and the critical event# cannot be cleared through software. sm bus slave subaddress decoding the temperature sensors physical address differs from the spd eeproms physical ad- dress: binary 0011 for a0, a1, a2, and rw#, where a2, a1, and a0 are the three slave subaddress pins and the rw# bit is the read/write flag. if the slave base address is fixed for the temperature sensor/spd eeprom, then the pins set the subaddress bits of the slave address, enabling the devices to be located any- where within the eight slave address locations. for example, they could be set from 30h to 3eh. 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 3: event# pin functionality time temperature critical alarm window (max) alarm window (min) event# interrupt mode event# comparator mode event# critical temperature only mode clears event hysteresis affects these trip points table 17: temperature sensor registers name address power-on default pointer register not applicable undefined capability register 0x00 0x0001 configuration register 0x01 0x0000 alarm temperature upper boundary register 0x02 0x0000 alarm temperature lower boundary register 0x03 0x0000 critical temperature register 0x04 0x0000 temperature register 0x05 undefined pointer register the pointer register selects which of the 16-bit registers is being accessed in subsequent read and write operations. this register is a write-only register. 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 18: pointer register bits 0C7 bit 7 6 5 4 3 2 1 0 0 0 0 0 register select register select register select register select table 19: pointer register bits 0C2 descriptions bit register 2 1 0 0 0 0 capability register 0 0 1 configuration register 0 1 0 alarm temperature upper boundary register 0 1 1 alarm temperature lower boundary register 1 0 0 critical temperature register 1 0 1 temperature register capability register the capability register indicates the features and functionality supported by the temper- ature sensor. this register is a read-only register. table 20: capability register (address: 0x00) bit 15 14 13 12 11 10 9 8 rfu rfu rfu rfu rfu rfu rfu rfu bit 7 6 5 4 3 2 1 0 rfu rfu rfu temperature resolution wider range precision has alarm and critical temperature table 21: capability register bit description bit description 0 basic capability 1: has alarm and critical trip point capabilities 1 accuracy 0: 2c over the active range and 3c over the monitor range 1: 1c over the active range and 2c over the monitor range 2 wider range 0: temperatures lower than 0c are clamped to a binary value of 0 1: temperatures below 0c can be read 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 21: capability register bit description (continued) bit description 4:3 temperature resolution 00: 0.5c lsb 01: 0.25c lsb 10: 0.125c lsb 11: 0.0625c lsb 15:5 0: must be set to zero configuration register table 22: configuration register (address: 0x01) bit 15 14 13 12 11 10 9 8 rfu rfu rfu rfu rfu hysteresis shutdown mode bit 7 6 5 4 3 2 1 0 critical lock bit alarm lock bit clear event event output status event output control critical event only event polarity event mode table 23: configuration register bit descriptions bit description notes 0 event mode 0: comparator mode 1: interrupt mode event mode cannot be changed if either of the lock bits is set. 1 event# polarity 0: active low 1: active high event# polarity cannot be changed if either of the lock bits is set. 2 critical event only 0: event# trips on alarm or critical temperature event 1: event# trips only if critical temperature is reached 3 event output control 0: event output disabled 1: event output enabled 4 event status 0: event# has not been asserted by this device 1: event# is being asserted due to an alarm window or critical temperature condition this is a read-only field in the register. the event caus- ing the event can be determined from the read tem- perature register. 5 clear event 0: no effect 1: clears the event when the temperature sensor is in the interrupt mode 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 23: configuration register bit descriptions (continued) bit description notes 6 alarm window lock bit 0: alarm trips are not locked and can be changed 1: alarm trips are locked and cannot be changed 7 critical trip lock bit 0: critical trip is not locked and can be changed 1: critical trip is locked and cannot be changed 8 shutdown mode 0: enabled 1: shutdown the shutdown mode is a power-saving mode that dis- ables the temperature sensor. 10:9 hysteresis enable 00: disable 01: enable at 1.5c 10: enable at 3c 11: enable at 6c when enabled, a hysteresis is applied to temperature movement around the trip points (see figure 4 (page 23)). as an example, if the hysteresis register is enabled to a delta of 6c, the preset trip points will toggle when the temperature reaches the program- med value. these values will reset when the tempera- ture drops below the trip points minus the set hysteresis level. in this case, this would be critical tem- perature minus 6c. the hysteresis is applied to both the above alarm win- dow and the below alarm window bits found in the read-only temperature register (see table 24 (page 23)). event# is also affected by this register. 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 4: hysteresis applied to temperature around trip points t h 1 t l 2 t h - hyst 3 t l - hyst below window bit above window bit notes: 1. t h is the value set in the alarm temperature upper boundary trip register. 2. t l is the value set in the alarm temperature lower boundary trip register. 3. hyst is the value set in the hysteresis bits of the configuration register. table 24: hysteresis applied to alarm window bits in the temperature register condition below alarm window bit above alarm window bit temperature gradient critical temperature temperature gradient critical temperature sets falling t l - hyst rising t h clears rising t l falling t h - hyst temperature format the temperature trip point registers and temperature readout register use a 2s comple- ment format to enable negative numbers. the least significant bit (lsb) is equal to 0.0625c or 0.25c, depending on which register is referenced. for example, assuming an lsb of 0.0625c: ? a value of 0x018c would equal 24.75c ? a value of 0x06c0 would equal 108c ? a value of 0x1e74 would equal C24.75c 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
temperature trip point registers the upper and lower temperature boundary registers are used to set the maximum and minimum values of the alarm window. lsb for these registers is 0.25c. all rfu bits in the register will always report zero. table 25: alarm temperature lower boundary register (address: 0x02) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 msb lsb rfu rfu alarm window upper boundary temperature table 26: alarm temperature lower boundary register (address: 0x03) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 msb lsb rfu rfu alarm window lower boundary temperature critical temperature register the critical temperature register is used to set the maximum temperature above the alarm window. the lsb for this register is 0.25c. all rfu bits in the register will always report zero. table 27: critical temperature register (address: 0x04) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 msb lsb rfu rfu critical temperature trip point temperature register the temperature register is a read-only register that provides the current temperature detected by the temperature sensor. the lsb for this register is 0.0625c with a resolu- tion of 0.0625c. the most significant bit (msb) is 128c in the readout section of this register. the upper three bits of the register are used to monitor the trip points that are set in the previous three registers. 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 28: temperature register (address: 0x05) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 above critical trip above alarm window below alarm window msb lsb temperature table 29: temperature register bit descriptions bit description 13 below alarm window 0: temperature is equal to or above the lower boundary 1: temperature is below alarm window 14 above alarm window 0: temperature is equal to or below the upper boundary 1: temperature is above alarm window 15 above critical trip point 0: temperature is below critical trip point 1: temperature is above critical trip point serial presence-detect data for the latest serial presence-detect data, refer to micron's spd page: www.micron.com/ spd . 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
module dimensions figure 5: 240-pin ddr3 rdimm 18.9 (0.744) 18.6 (0.732) pin 1 2.5 (0.098) d (2x) 2.3 (0.091) typ 5.0 (0.197) typ 123.0 (4.84) typ 1.0 (0.039) typ 0.8 (0.031) typ 0.75 (0.03) r (6x) 0.76 (0.03) r pin 120 front view 133.50 (5.256) 133.20 (5.244) 47.0 (1.85) typ 71.0 (2.79) typ 9.5 (0.374) typ back view pin 240 pin 121 1.37 (0.054) 1.17 (0.046) 4.0 (0.157) max 2.2 (0.087) typ 1.45 (0.057) typ 3.05 (0.12) typ 54.68 (2.15) typ 3.0 (0.118) 4x typ u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 notes: 1. all dimensions are in millimeters (inches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference only. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 2gb, 4gb (x72, ecc, dr) 240-pin 1.35v halogen-free ddr3 rdimm module dimensions pdf: 09005aef83aa70c0 kdf18c256_512x72pdz - rev. a 06/09 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.

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